Advances in very-large-scale integration (VLSI) design have increasingly relied on machine learning (ML) techniques to optimise performance, reduce manufacturing turnaround times and ensure high ...

Gate sizing is a fundamental technique in VLSI design, where the dimensions of transistors and gates are carefully adjusted to achieve optimal performance, minimise power consumption and reduce delay.

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...