For over 15 years, I've been a big proponent of hierarchical test. Hierarchical test is the commonly used term for creating DFT (design-for-test) features and test patterns at lower level circuit ...

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...

Test compression sounds like magic. Read on to learn how this trick is done. Large, complex ICs are viable because their design meets test as well as functional requirements. Design for test (DFT) was ...

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.

Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based ...

In New test points slash ATPG test pattern count, I described a new type of test point technology used with scan compression for device testing. The key benefit of using test points with embedded ...

It should come as no surprise that Moore's Law of regularly doubling chip capacity is having an impact on automatic test equipment (ATE) for ICs. ATE, of course, applies patterns of signals and checks ...

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...