EDN

Euro consortium demos SRAM using 32-nm process

LONDON — The PullNano consortium, a European collaborative research project set to to take CMOS down to the 32-nanometer and 22-nanometer manufacturing nodes, has devised a functional CMOS SRAM ...
NextBigFuture

Intel surrounding CMOS with new device architectures using new materials such as magnetic memories, Qubits, GaN transistors

Keynote speaker, IEEE Fellow Kevin Zhang, vice president of Intel’s Technology and Manufacturing Group, also Intel Director of Circuit Technology who led processor development from the 90-to-22 ...
Electronic Design

Crolles2 Alliance reveals ultra-dense SRAM cell in 45 nm conventional bulk CMOS

The Crolles2 Alliance, which includes Freescale Semiconductor, Philips and STMicroelectronics, has created six-transistor SRAM-bit cells with an area of less than 0.25 square microns, or about half ...
Nanowerk

IMEC presents functional 22nm SRAM cells fabricated using EUV technology

(Nanowerk News) Today, IMEC presented the world’s first functional 22nm CMOS SRAM cells made using EUV lithography. The 0.099µm2 SRAM cells are made with FinFETs and have both the contact and metal1 ...
Electronic Design

High-Density, Low-Power 32M CMOS SRAM

Alliance Memory today expands its line of legacy low-power CMOS SRAMs with a new 32M IC (2M x 16 / 4M x 8 switchable), the company's highest density low-power device to date. A line of legacy ...