EDN

Binary Clock Design

The Basic Stamp Homework Board (BSHWB) microcontroller, the PIC16C57, is a surprisingly useful and somewhat powerful microcontroller which I decided to choose for designing a binary clock, along with ...
Wired

OLED Digital Clock is Nothing But Numbers

You know those analog clocks which are nothing but a pair of hands on a spindle, distilling the function of the timekeeper down to its bare, concentrated essentials? The Black & White Clock is like ...
Semiconductor Engineering

Verification Of Multi-Clock Designs: The Bigger Picture

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this ...
EDN

Metastability and Clock Uncertainty in FPGA Designs

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...
Semiconductor Engineering

Conquer Placement And Clock Tree Challenges In HPC Designs

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.
Embedded

Dealing with PLL clock jitter in advanced processor designs: Part 3

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be ...