Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

Tektronix Component Solutions Increases ASIC and FPGA Test Capacity

Tektronix Component Solutions announced today the investment in five new Teradyne J750EX Semiconductor Test Systems to allow screening of a wider variety of complex ASICs, increase test capacity, and ...
Electronic Design

Product Innovations Aid MEMS Design and Test

Micro-electromechanical systems (MEMS) represent a key technology in the measurement space. Whether you are looking to design, produce, and test your own MEMS and associated circuitry or develop a ...
EDN

Design specification: The cornerstone of an ASIC collaboration

Engaging with an ASIC development partner can take many forms. The intended chip may be as simple as a microcontroller, as sophisticated as an AI-based edge computing system-on-chip (SoC), or even a ...
SpaceRef

SatixFy and Presto Engineering Partner to Test and Qualify Radiation Hardened Space-Grade ASICs for Next-Gen Satellite Communications

SatixFy Communications Ltd. (“SatixFy”) (NYSE AMERICAN: SATX), a leader in next-generation satellite communication systems based on in-house developed chipsets, is pleased to announce a strategic ...